Parallel Computers 2: Architecture, Programming and Algorithms, Volume 2Since the publication of the first edition, parallel computing technology has gained considerable momentum. A large proportion of this has come from the improvement in VLSI techniques, offering one to two orders of magnitude more devices than previously possible. A second contributing factor in the fast development of the subject is commercialization. The supercomputer is no longer restricted to a few well-established research institutions and large companies. A new computer breed combining the architectural advantages of the supercomputer with the advance of VLSI technology is now available at very attractive prices. A pioneering device in this development is the transputer, a VLSI processor specifically designed to operate in large concurrent systems. Parallel Computers 2: Architecture, Programming and Algorithms reflects the shift in emphasis of parallel computing and tracks the development of supercomputers in the years since the first edition was published. It looks at large-scale parallelism as found in transputer ensembles. This extensively rewritten second edition includes major new sections on the transputer and the OCCAM language. The book contains specific information on the various types of machines available, details of computer architecture and technologies, and descriptions of programming languages and algorithms. Aimed at an advanced undergraduate and postgraduate level, this handbook is also useful for research workers, machine designers, and programmers concerned with parallel computers. In addition, it will serve as a guide for potential parallel computer users, especially in disciplines where large amounts of computer time are regularly used. |
Contents
INTRODUCTION | 1 |
PIPELINED COMPUTERS | 117 |
MULTIPROCESSORS AND PROCESSOR ARRAYS | 245 |
PARALLEL LANGUAGES | 370 |
PARALLEL ALGORITHMS | 432 |
TECHNOLOGY AND THE FUTURE | 551 |
APPENDIX | 581 |
587 | |
611 | |
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Parallel Computers 2: Architecture, Programming, and Algorithms, Volume 2 Roger W. Hockney,C. R. Jesshope No preview available - 1988 |
Common terms and phrases
algorithm architecture arithmetic operations arithmetic units bandwidth bits boards buffer CDC CYBER chip circuit clock period common memory communication connection connection machine CRAY X-MP CYBER cyclic reduction data paths defined described diagram dimensions equation example execution fast Fourier transform FORTRAN gate hardware Hockney ICL DAP IEEE ILLIAC ILLIAC IV implementation INMOS input instruction streams integer Jesshope language log₂n logic loop machine main memory mapping matrix maximum Mbyte memory banks method Mflop/s microprocessors MIMD MIMD computer modules multiplication Mword OCCAM operands output parallel computers parameters perfect shuffle permutations pipelined pipelined computers problem processing elements processor array replicated routing scalar sequence sequential serial computer SIMD single solution STARAN storage structure supercomputer switch synchronisation transputer values vector computers vector instructions vector length vector operations vector processor vector registers vectorisation VLSI
Popular passages
Page 589 - Performance analysis of Poisson solvers on array computers, Infotech State of the Art Report: Supercomputers vol. 2, ed. CR Jesshope and RW Hockney (Maidenhead: Infotech Intl. Ltd.) 149-181.