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Parallel Computers 2: Architecture, Programming, and Algorithms, Volume 2
Roger W. Hockney,C. R. Jesshope
No preview available - 1988
addition applied architecture arithmetic operations arithmetic units binary bits Burroughs calculation CDC CYBER chip circuit clock period column compiler connection Control Data Corporation control unit crossbar switch CYBER cycle cyclic reduction DAP FORTRAN data paths defined described dimension equation evaluation example execution factor fast Fourier transform floating-point FORTRAN Fourier transform given Goodyear Aerospace hardware ICL DAP ILLIAC ILLIAC IV implementation indexing input integer iteration language log2 logic loop machine main memory mapping matrix multiplication maximum memory banks Mflop/s Mwords Mwords/s NASF operands organisation output parallel computers perfect shuffle performance permutations pipelined computers problem processing elements processor array recurrence result routing scalar selection sequential serial computer shift single ſº solution STARAN storage stored structure switch tridiagonal systems values vector instructions vector length vector operations vectorisation VECTRAN