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Parallel Computers 2: Architecture, Programming, and Algorithms, Volume 2
Roger W. Hockney,C. R. Jesshope
No preview available - 1988
addition applied architecture arithmetic operations arithmetic unit binary bits Burroughs calculation CDC CYBER chip clock period column compiler connection control unit crossbar switch CYBER cycle cyclic reduction DAP FORTRAN data paths defined delay described dimension equation evaluation example execution factor fast Fourier transform floating-point FORTRAN Fourier transform gate given Goodyear Aerospace hardware ICL DAP ILLIAC ILLIAC IV implementation indexing input integer iteration language log2 logic loop machine main memory mapping matrix multiplication maximum memory bandwidth memory banks Mflop/s Mwords Mwords/s NASF obtain operands organisation output parallel computers perfect shuffle performance permutations pipelined computers problem processing elements processor array recurrence result routing scalar selection serial computer shift single ſº solution STARAN stored structure subroutine switch tridiagonal systems values vector instructions vector length vector operations vectorisation VECTRAN words