CMOSET 2010 Semiconductor Technologies Track Presentation SlidesCMOS Emerging Technologies Research CMOS Emerging Technologies |
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2010 HRL Laboratories Analysis App Specific Architectures based Topology Bathtub Curve BCCCXXV TICINEN BiCMOS Channel Chip Circuits CMOS substrate Current Data Design Device DFARS as provided DHBT Digital DRAM Fat Tree Frequency Gate JFET Government Rights IEEE InP HBT InPInP interconnect IP core Itanium IUSS Sapere Aude JFET Jitter jitter amplification Jitter Modeling latency layer lifetime LOTHAR SIS VNIVERS Mesochronous metal Michael Scholles Microelettronica ST monitors Network Interface Network on Chip NoC Topology noise OLED-on-CMOS on-chip optimal PD PD PD photodetectors Photodiode provided in Contract Rights Reserved Sapere Aude GENERALE Sensor SEVENTH FRAMEWORK PROGRAMME shield silicon Simulation SIS VNIVERS STUDIUM solution SPAD STMicroelectronics Studio di Microelettronica Subject to Government substrate losses Superior Para IUSS switch synchronizer SystemC Tabu Tabu Search Temperature Thermal TICINEN GENERALE Time-gate Topology selection transistors Universitarie Stadi Superior Virtual Channels VNIVERS STUDIUM Studio Voltage Wafer X-FAB